View PI6C410B_1122338.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PI6C410B
Clock Generator for Intel PCI-Express Server Chipset
Features
* * * * * 14.318 MHz Crystal Input Selectable of 100, 133, 166, 200, 266, 333, and 400 MHz CPU Output Frequencies SMBus: Power Management Control Spread Spectrum support (-0.5% down spread) Packaging (Pb-free & Green): --56-Pin SSOP (V) --56-Pin TSSOP (A)
Description
PI6C410B is a high-speed, low-noise clock generator designed to work with Intel Server PCI-Express Chipset. The Spread Spectrum PLL based clock generator reduces EMI emission and supports a wide range of frequencies.
Jitter Performance
* * * * * < 85ps Cycle-to-Cycle CPU clock jitter < 350ps Cycle-to-Cycle 48MHz clock jitter < 500ps Cycle-to-Cycle PCI clock jitter < 125ps Cycle-to-Cycle SRC clock jitter < 1000ps Cycle-to-Cycle REF clock jitter
Output Features
* * * * * Four Pairs of Differential CPU Clocks Five Pairs of SRC Clocks Seven PCI Clocks One 48 MHz USB clock Two REF clocks
Skew Performance
* < 100ps Output to output CPU clock skew * < 500ps Output to output PCI clock skew * < 250ps Output to output SRC clock skew
Block Diagram
XT AL_IN XT AL_OUT XT AL OSC PLL 1 SDA SCL FS_A FS_B/TEST_MODE FS_C/TEST_SEL VTT_PWRGD# /PWRDWN IREF CONTROL SM Bus Logic DIV PLL 2 USB_48
Pin Configuration
VDD_PCI VSS_PCI PCI_0 PCI_1 PCI_2 PCI_3 VSS_PCI VDD_PCI PCIF_0 PCIF_1 PCIF_2 VDD_48 USB_48 VSS_48 VDD_SRC SRC_0 SRC_0# SRC_1# SRC_1 VSS_SRC SRC_2 SRC_2# SRC_3# SRC_3 VDD_SRC SRC_4 SRC_4# VDD_SRC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
REF [0:1] PCI [0:3] PCIF [0:2] DIV SRC [0:4] SRC [0:4]# CPU [0:3] CPU [0:3]#
DIV
FS_C / TEST_SEL REF_0 REF_1 VDD_REF XTAL_IN XTAL_OUT VSS_REF FS_B/TEST_MODE FS_A VDD_CPU CPU_0 CPU_0# VDD_CPU CPU_1 CPU_1# VSS_CPU CPU_2 CPU_2# VDD_CPU CPU_3 CPU_3# VDD_A VSS_A IREF NC VTT_PWRGD# / PWRDWN SDA SCL
1
PS8811A
02/01/06
PI6C410B Clock Generator for Intel PCI-Express Server Chipset Pin Descriptions
Pin Name REF[0:1] XTAL_IN XTAL_OUT CPU[0:3] & CPU[0:3]# SRC[0:4] & SRC[0:4]# PCIF[0:2] PCI[0:3] USB_48 FS_A FS_B / TEST_MODE FS_C / TEST_SEL IREF VTT_PWRGD# / PWRDWN SDA SCL VDD_PCI VDD_48 VDD_SRC VDD_CPU VDD_REF VSS_PCI VSS_48 VSS_SRC VSS_CPU VSS_REF VDD_A VSS_A Type Output Input Output Output Output Output Output Output Input Input Input Input Input I/O Input Power Power Power Power Power Ground Ground Ground Ground Ground Power Ground Pin No 54, 55 52 51 36, 37; 39, 40; 42, 43; 45, 46 16, 17; 18, 19; 21, 22; 23, 24; 26, 27 9, 10, 11 3, 4, 5, 6 13 48 49 56 33 31 30 29 1, 8 12 15, 25, 28 38, 44, 47 53 2, 7 14 20 41 50 35 34 Descriptions 3.3V 14.31818 MHz outputs 14.31818 MHz crystal input 14.31818 MHz crystal output Differential CPU outputs Differential Serial Reference Clock outputs 33 MHz clocks outputs (free running) 33 MHz clocks outputs 48 MHz clock output 3.3V LVTTL inputs for CPU frequency selection 3.3V LVTTL inputs for CPU frequency selection / Test Mode select: 0 = Hi-Z, 1 = Ref/N 3.3V LVTTL inputs for CPU frequency selection / Test Mode select if pulled to 3.3V when Vtt_Pwrgd# is asserted LOW External resistor connection for internal current reference 3.3V LVTTL Level sensitive strobe used to determine to latch the FS_A, FS_B/TEST_MODE and FS_C/TEST_SEL inputs (active low) / 3.3V LVTTL active high input for Power Down operation. SMBus compatible SDATA SMBus compatible SCLOCK 3.3V Power Supply for Outputs 3.3V Power Supply for Outputs 3.3V Power Supply for Outputs 3.3V Power Supply for Outputs 3.3V Power Supply for Outputs Ground for Outputs Ground for Outputs Ground for Outputs Ground for Outputs Ground for Outputs 3.3V Power Supply for PLL Ground for PLL
2
PS8811A
02/01/06
PI6C410B Clock Generator for Intel PCI-Express Server Chipset Functionality Frequency Selection
FS_C 1 0 0 0 0 1 1 1 FS_B 0 0 1 1 0 0 1 1 FS_A 1 1 1 0 0 0 0 1 CPU 100 MHz 133 MHz 166 MHz 200 MHz 266 MHz 333 MHz 400 MHz Reserved SRC 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz PCIF / PCI 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz REF 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz USB_48 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz Note 1 1 1 1 1 1 1 1
Notes: 1. Refer to DC Electrical Characteristics for FS_A, FS_B and FS_C (Vih_FS, Vil_FS) threshold levels
Test Mode Selection
TEST_MODE 1 0
Notes: 2. Test mode will occur where the SMBus Bit 6 of Byte 6 = 1, or FS_C/TEST_SEL is set to logic high level.
CPU REF/N Hi-Z
SRC REF/N Hi-Z
PCIF / PCI REF/N Hi-Z
REF REF Hi-Z
USB_48 REF/N Hi-Z
Note 2 2
PWRDWN Functionality
PWRDWN 0 1 CPU Normal Iref x 2 or Float CPU# Normal Float SRC Normal Iref x 2 or Float SRC# Normal Float PCIF / PCI 33 MHz Low REF 14.318 MHz Low USB_48 48 MHz Low
3
PS8811A
02/01/06
PI6C410B Clock Generator for Intel PCI-Express Server Chipset Serial Data Interface (SMBus)
PI6C410B is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit address and read/write bit as shown below.
Address Assignment
A6 1 A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W 0/1
Data Protocol
1 bit Start bit 7 bits Slave Addr 1 R/W 1 Ack 8 bits Register offset 1 Ack 8 bits Byte Count = N 1 Ack 8 bits Data Byte 0 1 Ack ... 8 bits Data Byte N-1 1 Ack 1 bit Stop bit
Note: 1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
Data Byte 0: Control Register
Bit 0 1 2 3 4 5 6 7 Descriptions SRC_0 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) SRC_1 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) SRC_2 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) SRC_3 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) SRC_4 Output Enable 1 = Enabled, 0 = Disabled (Hi-Z) Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW Power-Up Condition 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled Output(s) Affected SRC_0 SRC_1 SRC_2 SRC_3 SRC_4 Pin 17, 18 19, 20 22, 23 24, 25 26, 27 Source Pin NA NA NA NA NA
4
PS8811A
02/01/06
PI6C410B Clock Generator for Intel PCI-Express Server Chipset Data Byte 1: Control Register
Bit Descriptions Type Power-Up Condition Output(s) Affected Pin 3, 4, 5, 6, 9, 10, 11, 16, 17, 18, 19, 21, 22, 23, 24, 26, 27, 36, 37, 39, 40, 42, 43, 45, 46 45, 46 42, 43 Source Pin
0
Spread Spectrum 1 = On, 0 = Off CPU_0 output enable 1 = Enabled, 0 = Disabled (Hi-Z) CPU_1 output enable 1 = Enabled, 0 = Disabled (Hi-Z) Reserved CPU_2 output enable 1 = Enabled, 0 = Disabled (Hi-Z) CPU_3 output enable 1 = Enabled, 0 = Disabled (Hi-Z) REF0 Output Enable 1 = Enabled, 0 = Disabled REF1 Output Enable 1 = Enabled, 0 = Disabled
RW
0 = Spread off
CPU[0:3], SRC[0:4], PCI[0:3], PCIF[0:2]
NA
1 2 3 4 5 6 7
RW RW RW RW RW RW RW
1 = Enabled 1 = Enabled
CPU_0, CPU_0# CPU_1, CPU_1#
NA NA
1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled
CPU_2, CPU_2# CPU_3, CPU_3# REF_0 REF_1
39, 40 36, 37 55 54
NA NA NA NA
Data Byte 2: Control Register
Bit 0 1 2 3 4 5 6 7 Descriptions USB_48 Output Enable 1 = Enabled, 0 = Disabled PCIF_0 Output Enable 1 = Enabled, 0 = Disabled PCIF_1 Output Enable 1 = Enabled, 0 = Disabled PCIF_2 Output Enable 1 = Enabled, 0 = Disabled PCI_0 Output Enable 1 = Enabled, 0 = Disabled PCI_1 Output Enable 1 = Enabled, 0 = Disabled PCI _2 Output Enable 1 = Enabled, 0 = Disabled PCI _3 Output Enable 1 = Enabled, 0 = Disabled Type RW RW RW RW RW RW RW RW Power-Up Condition 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled Output(s) Affected USB_48 PCIF_0 PCIF_1 PCIF_2 PCI_0 PCI_1 PCI_2 PCI_3 Pin 13 9 10 11 3 4 5 6 Source Pin NA NA NA NA NA NA NA NA
5
PS8811A
02/01/06
PI6C410B Clock Generator for Intel PCI-Express Server Chipset Data Byte 3: Control Register
Bit 0 Descriptions SRC_0 Output Control 0 = Free Running 1 = Stopped with PCI_STOP# SRC_1 Output Control 0 = Free Running 1 = Stopped with PCI_STOP# SRC_2 Output Control 0 = Free Running 1 = Stopped with PCI_STOP# SRC_3 Output Control 0 = Free Running 1 = Stopped with PCI_STOP# SRC_4 Output Control 0 = Free Running 1 = Stopped with PCI_STOP# PCIF0 Output Control 0 = Free Running 1 = Stopped with PCI_STOP# PCIF1 Output Control 0 = Free Running 1 = Stopped with PCI_STOP# PCIF2 Output Control 0 = Free Running 1 = Stopped with PCI_STOP# Type RW Power-Up Condition 0 = Free running Output(s) Affected SRC_0, SRC_0# Pin 16, 17 Source Pin NA
1
RW
0 = Free running
SRC_1, SRC_1#
18, 19
NA
2
RW
0 = Free running
SRC_2, SRC_2#
21, 22
NA
3
RW
0 = Free running
SRC_3, SRC_3#
23, 24
NA
4
RW
0 = Free running
SRC_4, SRC_4#
26, 27
NA
5
RW
0 = Free running
PCIF_0
9
NA
6
RW
0 = Free running
PCIF_1
10
NA
7
RW
0 = Free running
PCIF_2
11
NA
6
PS8811A
02/01/06
PI6C410B Clock Generator for Intel PCI-Express Server Chipset Data Byte 4: Control Register
Bit 0 Descriptions CPU_0 Output Control 0 = Free Running 1 = Stopped with CPU_STOP# CPU_1 Output Control 0 = Free Running 1 = Stopped with CPU_STOP# CPU_2 Output Control 0 = Free Running 1 = Stopped with CPU_STOP# CPU_3 Output Control 0 = Free Running 1 = Stopped with CPU_STOP# CPU_0 Pwrdwn drive mode 1 = Hi-Z, 0 = Driven in Pwrdwn CPU_1 Pwrdwn drive mode 1 = Hi-Z, 0 = Driven in Pwrdwn CPU_2 Pwrdwn drive mode 1 = Hi-Z, 0 = Driven in Pwrdwn CPU_3 Pwrdwn drive mode 1 = Hi-Z, 0 = Driven in Pwrdwn Type RW Power-Up Condition 1 = Stopped with CPU_STOP# assertion 1 = Stopped with CPU_STOP# assertion 1 = Stopped with CPU_STOP# assertion 1 = Stopped with CPU_STOP# assertion 0 = Driven in power down 0 = Driven in power down 0 = Driven in power down 0 = Driven in power down Output(s) Affected CPU_0, CPU0# Pin 45, 46 Source Pin NA
1
RW
CPU_1, CPU1#
42, 43
NA
2
RW
CPU_2, CPU2#
39, 40
NA
3 4 5 6 7
RW RW RW RW RW
CPU_3, CPU3# CPU_0, CPU0# CPU_1, CPU1# CPU_2, CPU2# CPU_3, CPU3#
36, 37 45, 46 42, 43 39, 40 36, 37
NA NA NA NA NA
Data Byte 5: Control Register
Bit 0 1 2 3 4 5 Descriptions CPU_0 CPU_Stop drive mode 1 = Hi-Z, 0 = Driven in CPU Stop CPU_1 CPU_Stop drive mode 1 = Hi-Z, 0 = Driven in CPU Stop CPU_2 CPU_Stop drive mode 1 = Hi-Z, 0 = Driven in CPU Stop CPU_3 CPU_Stop drive mode 1 = Hi-Z, 0 = Driven in CPU Stop Reserved SRC_Pwrdwn drive mode 1 = Hi-Z, 0 = Driven in Pwrdwn SRC_Stop drive mode 1 = Hi-Z, 0 = Driven in PCI_STOP Reserved Type RW RW RW RW RW RW 0 = Driven in power down 0 = Driven in PCI_STOP SRC[0:4] & SRC[0:4]# SRC[0:4] & SRC[0:4]# 16, 17, 18, 19, 21, 22, 23, 24, 26, 27 16, 17, 18, 19, 21, 22, 23, 24, 26, 27 NA Power-Up Condition 0 = Driven in CPU_Stop 0 = Driven in CPU_Stop 0 = Driven in CPU_Stop 0 = Driven in CPU_Stop Output(s) Affected CPU_0, CPU0# CPU_1, CPU1# CPU_2, CPU2# CPU_3, CPU3# Pin 45, 46 42, 43 39, 40 36, 37 Source Pin NA NA NA NA
6 7
RW RW
NA
7
PS8811A
02/01/06
PI6C410B Clock Generator for Intel PCI-Express Server Chipset Data Byte 6: Control Register
Bit Descriptions FS_A Reflects the value of the FS_A pin sampled on power up 0 = FS_A was low during Vtt_Pwrgd# assertion FS_B Reflects the value of the FS_B pin sampled on power up 0 = FS_B was low during Vtt_Pwrgd# assertion FS_C Reflects the value of the FS_C pin sampled on power up 0 = FS_C was low during Vtt_Pwrgd# assertion PCI_Stop Output Control 0 = Enabled, all stoppable PCI and SRC clocks are stopped, 1 = Disabled REF Output Drive Strength 0 = 1X, 1 = 2X Reserved Test Clock Mode Entry Control 0 = Normal, 1 = REF/N or Hi-Z Test Clock Mode 0 = Hi-Z, 1 = REF/N Type Power-Up Condition Externally Selected Output(s) Affected Pin 36, 37, 39, 40, 42, 43, 45, 46 Source Pin
0
R
CPU[0:3]
NA
1
R
Externally Selected
CPU[0:3]
36, 37, 39, 40, 42, 43, 45, 46
NA
2
R
Externally Selected
CPU[0:3] All PCI & SRC clocks except PCIF and SRC clocks set to free-running REF_0, REF_1
36, 37, 39, 40, 42, 43, 45, 46 3, 4, 5, 6, 16, 17, 18, 19, 21, 22, 23, 24, 26, 27 54, 55
NA
3
RW
1 = Disabled
NA
4 5 6 7
RW RW RW RW
1 = 2X
NA
0 = Disabled 0 = Hi-Z NA
Data Byte 7: Pericom ID Register
Bit 0 1 2 3 4 5 6 7 Revision Code Vendor ID Descriptions Type R R R R R R R R Power-Up Condition 0 0 0 0 1 0 1 0 Output(s) Affected NA NA NA NA NA NA NA NA Pin NA NA NA NA NA NA NA NA
8
PS8811A
02/01/06
PI6C410B Clock Generator for Intel PCI-Express Server Chipset Power Down (PWRDWN assertion)
PWRDWN CPU, 133MHz CPU#, 133MHz SRC, 100MHz SRC#, 100MHz USB, 48MHz PCI, 33MHz REF, 14.318MHz
Figure 1. Power down sequence
Power Down (PWRDWN De-assertion)
Tstable < 1.8ms PWRDWN CPU, 133MHz CPU#, 133MHz SRC, 100MHz SRC#, 100MHz USB, 48MHz PCI, 33MHz REF, 14.318MHz Tdrive_PWRDWN < 300us, >200mV
Figure 2. Power down de-assert sequence
9
PS8811A
02/01/06
PI6C410B Clock Generator for Intel PCI-Express Server Chipset Tristate Specifications CPU & SRC Tristate clock truth table
Signal CPU[0:3], SRC[0:4], Pwrdwn pin 0 1 1 Pwrdwn Tristate Bit X 0 1 Stoppable Outputs Running Driven @ Iref x 2 Tristate Non-stop Outputs Running Driven @ Iref x 2 Tristate
Spread Spectrum Specifications
Supports Spread Spectrum clocking and can be enabled and disabled via SMBus control. The maximum Spread Spectrum Modulation is -0.5% down spread with frequency from 30KHz to 33K Hz. SSC ON CPU @ 399.000MHz CPU @ 332.500MHz CPU @ 266.000MHz CPU @ 199.500MHz CPU @ 166.250MHz CPU @ 133.000MHz CPU @ 99.750MHz SRC @ 99.750MHz PCIF / PCI @ 33.250MHz Tperiod Min 2.4993 2.9991 3.7489 4.9985 5.9982 7.4978 9.9970 9.9970 29.9910 Max 2.5133 3.0160 3.7700 5.0266 6.0320 7.5400 10.0533 10.0533 30.1598 SSC OFF CPU @ 400.000MHz CPU @ 333.333MHz CPU @ 266.666MHz CPU @ 200.000MHz CPU @ 166.666MHz CPU @ 133.333MHz CPU @ 100.000MHz SRC @ 100.000MHz PCIF / PCI @ 33.333MHz Tperiod Min 2.4993 2.9991 3.7489 4.9985 5.9982 7.4978 9.9970 9.9970 29.9910 Max 2.5008 3.0009 3.7511 5.0015 6.0018 7.5023 10.0030 10.0030 30.0090 ns Unit
Crystal Recommendations
Frequency 14.31818 MHz Cut AT Loading Parallel Load Cap 20pF Drive Max. 0.1mW Shunt Cap Max. 5pF Motional Cap Max. 0.016pF Tolerance Max. 50ppm Stability Max. 50ppm Aging Max. 5ppm
Notes: 1. External trim capacitors (Ce) are required by using this formula Ce = 2*CL - (Cs + Ci). Typical Ce = 33pF when Crystal Load = 20pF, Trace capacitance (Cs) = 2.8pF and XTAL pins capacitance = 4.5pF.
10
PS8811A
02/01/06
PI6C410B Clock Generator for Intel PCI-Express Server Chipset Current-mode output buffer characteristics of CPU and SRC
VDD (3.3V 5%) Slope ~ 1/RO RO IOUT ROS IOUT VOUT = 0.85V max 0V 0.85V
Figure 3. Simplified diagram of current-mode output buffer
Host Clock Buffer characteristics
Symbol RO ROS VOUT Minimum 3000 unspecified N/A Maximum N/A unspecified 850mV
Current Accuracy
Symbol IOUT Conditions VDD = 3.30 5% Configuration RREF = 475 1% IREF = 2.32mA Load Nominal test load for given configuration Min. -12% INOMINAL Max. +12% INOMINAL
Note: 1. INOMINAL refers to the expected current based on the configuration of the device.
Host Clock Output Current
Board Target Trace/Term Z 100 (100 differential 8% coupling ratio) Reference R, IREF = VDD/(3xRr) RREF = 475 1%, IREF = 2.32mA Output Current IOH = 6 x IREF VOH @ Z 0.7V @ 50
11
PS8811A
02/01/06
PI6C410B Clock Generator for Intel PCI-Express Server Chipset Absolute Maximum Ratings (Over operating free-air temperature range)
Symbol VDD_A VDD VIH VIL Ts VESD Parameters 3.3V Core Supply Voltage 3.3V I/O Supply Voltage Input High Voltage Input Low Voltage Storage Temperature ESD Protection -0.5 -65 2000 150 C V Min. -0.5 -0.5 Max. 4.6 4.6 4.6 V Units
Note: 1. Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
DC Electrical Characteristics (VDD = 3.35%, VDD_A = 3.35%)
Symbol VDD_A VDD VIH VIL IIK VIH_FS VIL_FS VOH VOL Parameters 3.3V Core Supply Voltage 3.3V I/O Supply Voltage 3.3V Input High Voltage 3.3V Input Low Voltage Input Leakage Current 3.3V Input High Voltage 3.3V Input Low Voltage 3.3V Output High Voltage 3.3V Output Low Voltage IOH = -1mA IOL = 1mA CPU, SRC: IOH = 6 x Iref, Iref = 2.32mA IOH Output High Current USB REF, PCI USB IOL Output Low Current REF, PCI Cin Cxtal Cout Lpin IDD ISS ISS Ta Input Pin Capacitance Xtal Pin Capacitance Output Pin Capacitance Pin Inductance Power Supply Current Power Down Current Power Down Current Ambient Temperature
12
Condition
Min. 3.135 3.135
Max. 3.465 3.465 VDD + 0.3 0.8 +5 VDD + 0.3 0.35 0.4
Units
VDD 0 < VIN < VDD
2.0 VSS - 0.3 -5 0.7 VSS - 0.3 2.4 12.2
V
A V V V V
15.6 -29 -23 -33 -33 29 27 30 38 3 3 5 6 6 7 nH mA C
PS8811A 02/01/06
VOH = 1.0V VOH = 3.135V VOH = 1.0V VOH = 3.135V VOL = 1.95V VOL = 0.4V VOL = 1.95V VOL = 0.4V
mA
pF
VDD = 3.465V, FCPU = 400MHz Driven outputs Tristate outputs 0
500 85 12 70
PI6C410B Clock Generator for Intel PCI-Express Server Chipset AC Switching Characteristics (VDD = 3.35%, VDD_A = 3.35%)
Symbol Trise / Tfall Trise / Tfall Trise / Tfall Trise / Tfall Tskew Tskew Tskew Tjitter Tjitter Tjitter Tjitter Tjitter VHIGH VLOW VCROSS VCROSS TDC TDC Tstable Tdrive Pwrdwn Trise / Tfall Pwrdwn Outputs CPU, SRC PCI/PCIF, REF USB CPU, SRC CPU SRC PCI/PCIF, REF CPU SRC PCI/PCIF USB REF CPU, SRC CPU, SRC CPU, SRC CPU, SRC CPU, SRC REF, USB, PCI/PCIF Parameters Rise and Fall Time (measured between 0.175V to 0.525V) Rise/Fall Edge Rate (measured between 0.8V to 2.0V) Rise/Fall Edge Rate (measured between 0.8V to 2.0V) Rise and Fall Time Variation CPU - CPU Skew SRC - SRC Skew PCI - PCI Skew / REF - REF Skew (measured at 1.5V) Cycle - Cycle Jitter Cycle - Cycle Jitter Cycle - Cycle Jitter (measured at 1.5V) Cycle - Cycle Jitter (measured at 1.5V) Cycle - Cycle Jitter (measured at 1.5V) Voltage High including overshoot Voltage Low including undershoot Absolute crossing point voltages Total Variation of Vcross over all edges Duty Cycle Duty Cycle (measured at 1.5V) All clock stabilization from power-up Differential output enable after PwrDwn de-assertion PwrDwn rise and fall time 45 45 660 -300 250 550 140 55 55 <1.8 300 5.0 % ms s ns Min 175 1.0 1.0 Max. 700 4.0 V/ns 2.0 125 100 250 500 85 125 500 350 1000 1150 mV ps ps 6 3, 4 3, 5 3, 5 6 3, 5 3, 5 6 6 6 3, 4 3, 4 3, 4 3, 4 3, 5 6 Fig 2 Fig 2 Units ps Notes 3, 4 6
Notes: 3. Test configuration is Rs = 33.2, Rp = 49.9, and 2pF. 4. Measurement taken from Single Ended waveform. 5. Measurement taken from Differential waveform. 6. Two Loads for PCI/PCIF and USB. Three loads for REF. RS=125%, Max 20" into 5pF load with 60 impedance.
13
PS8811A
02/01/06
PI6C410B Clock Generator for Intel PCI-Express Server Chipset Configuration test load board termination
Rs 33 5% PI6C410B Clock TLA Clock# TLB Rp 49.9 1% Rp 49.9 1% 2pF 5% 2pF 5%
Rs 33 5%
475 1%
Note: 1. Maximum 10" trace length for CPU outputs at 200 MHz. Maximum 16" trace length for SRC outputs at 100 MHz.
Figure 4. Configuration test load board termination
Packaging Mechanical: 56-Pin, 240-mil wide TSSOP (A)

14
PS8811A
02/01/06
PI6C410B Clock Generator for Intel PCI-Express Server Chipset Packaging Mechanical: 56-Pin, 300-mil wide SSOP (V)
56
.291 .299 7.39 7.59
.396 .416 10.06 10.56
Gauge Plane
.010 0.25
1
.02 .04 0.51 1.01
.720 18.29 .730 18.54
.008 0.20 Nom.
.015 0.381 x 45 .025 0.635
.110 2.79 Max
.025 BSC 0.635
X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS
.008 .0135 0.20 0.34
0-8
.008 0.20 .016 0.40
Ordering Information(1,2,3)
Ordering Code PI6C410BAE PI6C410BVE Package Code A V Package Description Pb-free & Green, 56-pin TSSOP Pb-free & Green, 56-pin SSOP
Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. Number of transistors = TBD 3. E = Pb-free and Green
Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com
15
PS8811A 02/01/06

▲Up To Search▲

Price & Availability of PI6C410B

	To Download PI6C410B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .